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SUMMIT
MICROELECTRONICS, Inc.
SMS2902/SMS2904/SMS2916
Voltage Supervisory Circuit With Watchdog Timer
FEATURES * Precision Voltage Monitor - VCC Supply Monitor - Complementary reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required *Watchdog Timer - 1600 ms, internal * Two Wire Serial Interface (I2CTM) * Extended Programmable Functions available on SMS24 * High Reliability - Endurance: 100,000 erase/write cycles - Data retention: 100 years * 8-Pin SOIC Packages
OVERVIEW The SMS29xx is a power supervisory circuit that monitors VCC and will generate complementary reset outputs. The reset pins also act as I/Os and may be used for signal conditioning. The SMS29xx also has an on-board watchdog timer. The SMS29xx integrates a nonvolatile serial memory. It features the industry standard I 2 C serial interface allowing quick implementation in an end-users' system.
BLOCK DIAGRAM
VCC 8
SCL SDA
6 5
NONVOLATILE MEMORY ARRAY
WRITE CONTROL
PROGRAMMABLE RESET PULSE GENERATOR
2
RESET#
+ -
VTRIP
RESET CONTROL
7 WDI# 1 1.26V WATCHDOG TIMER
RESET
4 GND
2028 T BD 2.0
SUMMIT MICROELECTRONICS, Inc.
*
300 Orchard City Drive, Suite 131
*
Campbell, CA 95008
*
Telephone 408-378-6461
*
Fax 408-378-6586
*
www.summitmicro.com
(c) SUMMIT MICROELECTRONICS, Inc. 2000 2028 5.1 8/2/00
Characteristics subject to change without notice
1
SMS2902/SMS2904/SMS2916
PIN CONFIGURATIONS PIN NAMES Symbol WDI# Pin 1 Description Watchdog Input /a high to low transition will clear the watchdog timer Active Low RESET Input/Output No Connect, tie to ground or leave open Analog and Digital Ground Serial Memory Input/ Output data line Serial Memory clock input Active High RESET Input/ Output Supply Voltage
2028 PGM T1.1
8-Pin SOIC
WDI# RESET# NC GND
1 2 3 4
8 7 6 5
VCC RESET SCL SDA
RESET# NC GND SDA SCL RESET VCC
2 3 4 5 6 7 8
2028 T PCon 2.0
CAPACITANCE TA = 25C, f = 100KHz Symbol CIN LOUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF
2028 PGM T2..0
tR tF
tH IGH
tLOW
tSU:STO
SCL
tSU:SDA tHD:SDA tHD:DAT tSU:DAT tBUF
SDA In
tDH tAA
SDA Out
2028 ILL5.0
FIGURE 1. SERIAL BUS TIMING DIAGRAM
2028 5.1 8/2/00
2
SMS2902/SMS2904/SMS2916
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ............................................................................................................................... -40C to +85C Storage Temperature ..................................................................................................................................... -65C to +125C Soldering Temperature (less than 10 seconds) ................................................................................................................... 300C Supply Voltage ............................................................................................................................................................. 0 to 6.5V Voltage on Any Pin ....................................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Commercial Industrial Min 0C -40C Max +70C +85C
2028 PGM T3.0
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol ICC ISB ILI ILO VIL VIH VOL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC S0, S1, S2, SCL, SDA, RESET# S0, S1, S2, SCL, SDA, RESET IOL = 3mA SDA 0.7xVCC 0.4 VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 0.3xVCC Units mA mA A A A A V V V
2028 PGM T4.0
AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol Parameter SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock to Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Spike Width @ SCL, SDA Inputs Write Cycle Time Noise Suppression Time Constant SCL Low to SDA Data Out Valid SCL Low to SDA Data Out Change Before New Transmission Conditions
2.7V to 4.5V Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 250 0 100 10 3.5 Max 100
4.5V to 5.5V Min Max 400 1.3 0.6 1.3 0.6 0.6 0.6 0.2 0.2 300 300 100 0 100 10 0.9 Units KHz s s s s s s s s ns ns ns ns ns ms
2028 PGM T5.0
fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT
TI
tWR
2028 5.1 8/2/00
3
SMS2902/SMS2904/SMS2916
tGLITCH
VTRIP VRVALID
tRPD tPURST tPURST
VCC
RESET#
tRPD
RESET
2028 T fig02 2.0
FIGURE 2. RESET OUTPUT TIMING
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA=-40C to +85C
Symbol VTRIP Parameter Reset Trip Point Part no. Suffix A (or) Blank B 2.7 Min. 4.250 4.50 2.55 Typ. 4.375 4.625 2.65 200 Max. 4.5 4.75 2.75 5 1 30 0.4 VCC-.75 1.20 1.20 1.20 1.20 1.25 1.25 1.25 1.25 1.30 1.30 1.30 1.30 5 5 1600 Unit V V V ms s V ns V V V V V V s s ms
tPURST tRPD VRVALID tGLITCH VOLRS VOHRS VULH VUHL VOLH VOHL tVD1 tVD2 tWDTO
Reset Timeout VTRIP to RESET Output Delay RESET Output Valid to VCC min. Guarantee Glitch Reject Pulse Width note 1 RESET Output Low Voltage IOL = 1mA RESET High Voltage Output IOH = 800A VSENSE Under-voltage threshold low to high VSENSE Under-voltage threshold high to low VSENSE Over-voltage threshold low to high VSENSE Over-voltage threshold high to low Delay to VLOW Active Delay to VLOW Released Watchdog timeout Period
2028 5.1 8/2/00
4
SMS2902/SMS2904/SMS2916
WDI#
< tWDTO tWDTO tPURST
RESET#
WDI#
tWDTO tPURST tWDTO tPURST
RESET#
2028 T fig03 2.0
FIGURE 3. WATCHDOG TIMER TIMING DIAGRAM
RESET# (in) RESET# (out) tPURST tPURST RESET (out)
2028 T fig04 2.0
FIGURE 4. RESET AS AN INPUT FUNCTION
2028 5.1 8/2/00
5
SMS2902/SMS2904/SMS2916
PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. RESET# - RESET# is an active low output. Whenever VCC is below VTRIP the SMS29xx will drive the RESET# pin to ground. The RESET# pin is an I/O and can be used as a reset input. Refer to Figure 1 as an example use of this pin as a push button switch debounce circuit. It should be noted this is an open drain output and an external pull-up resistor tied to VCC is needed for proper operation. RESET -- RESET is an active high output. Whenever VCC is below VTRIP the SMS29xx will drive the RESET pin to the VCC rail. The RESET pin is an I/O and can be used as a reset input. It should be noted this is an open drain output and an external pull-down resistor tied to ground is needed for proper operation. WDI# - The WDI# input is used as a hardware method of clearing the watchdog timer. A high to low transition on this pin will clear the watchdog timer. If a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active. ENDURANCE AND DATA RETENTION The SMS29xx is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. Reset Controller Description The SMS29xx provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for tPURST (200 msec) after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when VCC falls below VTRIP. The RESET pins are I/Os; therefore, the SMS29xx can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit. WATCHDOG TIMER OPERATION The SMS29xx has a watchdog timer with a programmable timeout period. Whenever the watchdog times out it will generate a reset output on both RESET# and RESET. Any transition on WDI will clear the watchdog timer. If a transition is not detected within tWDTO seconds the watchdog will time out and force the reset outputs active.
2028 5.1 8/2/00
6
SMS2902/SMS2904/SMS2916
SCL from Master Data Output from Transmitter Data Output from Receiver Start Condition
1
8
9
tAA
tAA
ACKnowledge
2028 ILL7.0
FIGURE 5. ACKNOWLEDGE RESPONSE FROM RECEIVER
CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition. START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the "START" condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the "STOP" condition . DEVICE OPERATION The SMS29xx is a 2K/4K/16K serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a "transmitter" and any device which receives data as a "receiver." The device controlling data transmission is called the "master" and the controlled device is called the "slave." In all cases, the SMS29xx will be a "slave" device, since it never initiates any data transfers. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 5). The SMS29xx will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the SMS29xx will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode, the SMS29xx transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the SMS29xx will continue to transmit data. If an ACKnowledge is not detected, the SMS29xx will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (`1010') (see figure 6).
DEVICE IDENTIFIER
1
0
1
0
A 10 *
A 9 *
A 8 **
R/W
2028 ILL8.1 * = 2916 only ** = 2904 only FIGURE 6. SLAVE ADDRESS BYTE
2028 5.1 8/2/00
7
SMS2902/SMS2904/SMS2916
The next three bits are the high order address bits on the 2904 and 2916 and are "Don't Care" on the 2902. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to "1," a read operation is selected; when set to "0," a write operation is selected. WRITE OPERATIONS The SMS29xx allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte WRITE Upon receipt of both the slave address and word address, the SMS29xx responds with an ACKnowledge for each. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the SMS29xx begins the internal write cycle. While the internal write cycle is in progress, the SMS29xx inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 7 for the address, ACKnowledge and data transfer sequence. Page WRITE The SMS29xx is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more bytes of data. After the receipt of each byte, the SMS29xx will respond with an ACKnowledge. The SMS29xx automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will "roll over," and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 7 for the address, ACKnowledge and data transfer sequence.
Acknowledges Transmitted from SMS29xx to Master Receiver
If single byte-write only, Stop bit issued here.
Acknowledges Transmitted from SMS29xx to Master Receiver
SDA Bus Activity
1010
AAXR 10 9 W
A C Word Address K
AAAAAAAA 76543210
A C K
Data Byte n
A C K
A
Data Byte n+1 C
K
DDDDDDDD 76543210
Data Byte n+15 C
K
DDDDDDDD 76543210
A
AA X 10 9
0
DDDDDDDD 76543210
S T Device Type A R Address Read/Write T 0= Write
S T O P
Slave Address
Master Sends Read Request to Slave Master Writes Word Address to Slave Master Writes Data to Slave Master Writes Data to Slave Master Writes Data to Slave
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver
2028 ILL9.1
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Shading Denotes SMS29xx SDA Output Active
FIGURE 7. PAGE/BYTE WRITE MODE
2028 5.1 8/2/00
8
SMS2902/SMS2904/SMS2916
Acknowledge Polling When the SMS29xx is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 8).
Internal WRITE Cycle In Progress; Begin ACK Polling
READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to "1." There are four different read options: 1. 2. 3. 4. Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read
Issue Start
Issue Slave Address and R/W = 0
Issue Stop
Current Address Byte Read The SMS29xx contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the SMS29xx receives the slave address field with the R/W bit set to "1," it issues an acknowledge and transmits the 8bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the SMS29xx discontinues data transmission. See Figure 9 for the address acknowledge and data transfer sequence.
ACK Returned?
No
Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Yes Issue Byte Address Issue Stop No
Proceed with WRITE
Await Next Command
2028 ILL10.0
FIGURE 8. ACKNOWLEDGE POLLING
SDA Bus Activity
1
X XXR W
A C K
Data Byte
1010
S Device T Type A Address R T
1
DDDDDDDD 76543210
1
S T O P
Read/Write 1= Read
Slave Address
Master sends Read request to Slave
Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Slave Transmitter to Master Receiver
Master Transmitter to Slave Receiver
Shading Denotes SMS29xx SDA Output Active
2028 ILL11.1
FIGURE 9. CURRENT ADDRESS BYTE READ MODE
2028 5.1 8/2/00
9
SMS2902/SMS2904/SMS2916
Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS29xx to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The SMS29xx will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The SMS29xx discontinues data transmission and reverts to its standby power mode. See Figure 10 for the address, acknowledge and data transfer sequence.
SDA Bus Activity
1010
S T Device Type A Address R T
xx AAXR W 10 9
A C K
Word Address
A C K
XXXR W
A C K
Data Byte
AA 10 9 X
0
AAAA 7654
AA 32
AA 10
1010
S T Device Type A Address R T
1
D DD DD DD D 7 65 43 21 0
1
S T O P
Read/Write 0= Write
Read/Write 1= Read
Slave Address
Master sends Read request to Slave Master Writes Word Address to Slave
Slave Address
Master Requests Data from Slave
Lack of ACK (low) from Master determines last data byte to be read
Slave sends Data to Master
Master Transmitter to Slave Receiver Shading Denotes SMS29xx SDA Output Active
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
2028 ILL12.1
FIGURE 10. RANDOM ADDRESS BYTE READ MODE
2028 5.1 8/2/00
10
SMS2902/SMS2904/SMS2916
Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the SMS29xx. The SMS29xx continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will `roll-over' and the memory will continue to output data. See Figure 11 for the address, acknowledge and data transfer sequence.
Acknowledges from SMS29xx
Acknowledge from Master Receiver
Lack of Acknowledge from Master Receiver
SDA Bus Activity
AA R X 10 9 W
A C Word Address K
AAAAAAAA 76543210
A C K
XXX
R W
A C K
A
First Data Byte C
K
DD DD DD DD 76 54 32 10
Last Data Byte
1 0 1 0 10
S T Device A Type R Address T
AA 9X
0
1010
S T Device A Type R Address T
1
DD DD DD DD 76 54 32 10
1
S T O P
Read/Write 0= Write
Read/Write 1= Read
Slave Address
Master sends Read request to Slave Master Writes Word Address to Slave
Slave Address
Master Requests Data from Slave Slave sends Data to Master
Lack of ACK (low) determines last data byte to be read
Slave sends Data to Master
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Master Transmitter to Slave Receiver
2028 ILL13.1
Shading Denotes SMS29xx SDA Output Active FIGURE 11. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
2028 5.1 8/2/00
11
SMS2902/SMS2904/SMS2916
PB_RST# VCC = 3.0V or 5.0V
ALE
SMS29xx
WDI# RESET# NC GND VCC RESET SCL SDA
8051 Type MCU
RST SCL (P0.0) SDA (P0.1)
I2C Peripheral
RESET# SCL SDA
2028 T fig12 2.0
TYPICAL APPLICATION USING DUAL RESET FUNCTION AND WATCHDOG TIMER
PB_RST# 5.0VDC
SMS29xx Z80
WDI# RESET# NC GND VCC RESET SCL SDA I/O I/O
DECODER
RST#
2028 T fig13 2.0
TYPICAL APPLICATION CONFIGURATION USING SYSTEM DECODE LOGIC TO RESET WDI
5.0VDC VCC
1232
PBRST# TOL GND VCC ST# RST# RST ALE RST ALE
SMS29xx
WDI# RESET# NC GND VCC RESET SCL SDA
24C16
I/O I/O SCL SDA
8051 Family Part
8051 Family Part RST
I/O I/O
GND
2028 T fig14 2.0
From This
2028 5.1 8/2/00
To This
12
SMS2902/SMS2904/SMS2916
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP. .050 (1.270) TYP. 8 Places
.157 (4.00) .150 (3.80)
.275 (6.99) TYP.
1 .196 (5.00) .189 (4.80)
.030 (.762) TYP. 8 Places
.061 (1.75) .053 (1.35)
FOOTPRINT
.020 (.50) x45 .010 (.25)
.0192 (.49) .0138 (.35)
.0098 (.25) .004 (.127) .05 (1.27) TYP.
.035 (.90) .016 (.40)
.244 (6.20) .228 (5.80)
8pn JEDEC SOIC ILL.2
13
2028 5.1 8/2/00
SMS2902/SMS2904/SMS2916
ORDERING INFORMATION
SMS2902 Base Part Number Package S = SOIC
S
A VTRIP A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V
2028-02 Tree 2.0
SMS2904 Base Part Number Package S = SOIC
S
A VTRIP A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V
2028-04 Tree 2.0
SMS2916 Base Part Number Package S = SOIC
S
A VTRIP A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V
2028-16 Tree 2.0
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 2000 SUMMIT Microelectronics, Inc.
I2C is a trademark of Philips Corporation.
2028 5.1 8/2/00
14

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